The present invention relates generally to the field of semiconductor chip testing, and more particularly to a circuit for generating memory addresses for a CN.sup.2 memory test (where C is the multicycle rate for the N.sup.2 test and is an integer).
Semiconductor memory chips are commonly tested to determine the speed of access between different address locations in the memory. Each individual transition between address locations comprises the operation of de-selecting the current address location and selecting the new address location, and then measuring the time required for the data at this new memory address to appear at the memory output terminals. Such memory access timing is required for each possible memory address transition because a late transition of data to the memory outputs would cause the wrong data to be operated on in the system.
N.sup.2 addressing is a preferred technique for testing memory transitions because it permits the characterization of the effects of each address on every other address in a memory array. The standard for generating this pattern has been to create a SCAN where all `AWAY` addresses are tested to a fixed `HOME` address. At the completion of this SCAN, a new `HOME` address is selected and the procedure repeated until each address in the array has been the `HOME` address. The address transitions required to generate such an N.sup.2 pattern are illustrated in Table 1, where N is the number of addresses in the array. A SCAN appears as an entire row in this table and the entire table consists of N SCANS. By definition, an N.sup.2 test requires N.sup.2 distinct transition to occur. From Table 1, each transition requires 2 addresses. Consequently, the standard N.sup.2 test requires 2N.sup.2 memory cycles. However, the 2N.sup.2 required memory cycles make the test time-consuming and inefficient.
The invention as claimed is intended to remedy this problem.
The advantage offered by the present invention is that it allows a 2N.sup.2 memory test to be performed in N.sup.2 +1 memory cycles, thereby significantly increasing the speed of the test. A further advantage offered by the present invention is that it can be implemented in hardware, eliminating the need for buffer storage of the memory address sequence. A yet further advantage of the present invention is that the address generation hardware can be placed directly on a semiconductor chip.